1. Technical Field
The present disclosure relates to a technique for controlling communication buses in a bus system including networked communication buses (distributed buses) provided in a semiconductor integrated circuit.
2. Description of the Related Art
When developing a system having semiconductor circuits, there is a demand for reducing the cost of implementation/development by completing the system in a short amount of time by freely combining together a plurality of semiconductor circuits. For example, it is possible to develop a system at low cost by making modules of semiconductor circuits in the form of chips in advance so that one can utilize chips developed in the past as external chips (off-chips) for modules that do not need to be newly developed.
However, in order to efficiently utilize modules developed in the past, the bus system for connecting together semiconductor circuits and transmitting communication data therebetween needs to have a flexibility in settings (granularity of freedom in settings). A plurality of masters (nodes) are present in each module, and each master performs data communication with a different quality requirement with a slave such as a memory element. The “quality requirement” as used herein refers to the delay or the throughput to be guaranteed, for example.
NoC (Network-on-Chip) techniques, capable of reducing the number of buses, are used for bus systems for transmitting data communication traffic flows. With NoC, buses are connected via routers (relay devices). Since traffic flows having different quality requirements are transmitted sharing the same bus, the transmission is controlled while varying the manner of sending for each quality requirement. In order to ensure an optimal level of transmission performance (delay and throughput for the transmission) depending on the combination of masters, one needs to be able to flexibly set the manner of sending. Thus, with flexible bus systems having a plurality of settings variations, such as where settings are done for each module or settings are done for each master, it is possible to develop more efficiently. In order to combine a plurality of chips together, chips need to be connected together by low-speed buses with which all the chips are compatible. Therefore, it is necessary to make settings while taking into consideration significant transmission delays to be experienced when passing through the low-speed links. Note that a bus with a significant delay will be hereinafter referred to as a “low-speed link”. A low-speed link may be determined relatively with respect to other buses, or may be determined as being a bus that does not satisfy required transmission performance. For example, a bus having a high delay is included as a low-speed link even if the bus's transmission quantity per unit time is large.
Japanese Laid-Open Patent Publication No. 2004-56328 discloses a conventional relay device. FIG. 1 shows a configuration of a conventional relay device.
The conventional relay device is provided with three types of buffers. The three types of buffers are dedicated buffers for storing traffic flows transmitted from Bus Masters A to C, respectively. The type of the traffic flow to be sent (the quality to be required) is determined for each of Bus Masters A to C. For example, they are the quality ensured type traffic flow (A), the best-effort low-delay type traffic flow (B), and the best-effort type traffic flow (C). The three types of buffers are provided for controlling the sending schedule while distinguishing these traffic flows from one another. Traffic flows, having arrived at Relay Device R, are once stored separately in the respective dedicated buffers. Note that traffic flows are transmitted in the form of packets.
The relay device controls the sending schedule of each packet according to the priority of the quality requirement of each traffic flow, and outputs the packet from the respective dedicated buffer according to the determined sending schedule. The arbiter of the relay device connects buffers to the output port preferentially in a descending order of the level of quality requirement of the buffers. In this manner, the sending schedule can be controlled according to the level of quality requirement of each traffic flow.